The present invention relates to a method of packaging chip elements such as semiconductor devices and optical devices onto a wafer-board, and more particularly to a of packaging chip elements onto a wafer-board by a flip-chip bonding method.
In recent years, a flip-chip bonding has been attractive as being effective for satisfying the requirements for scaling down of the package and a reduction in thickness of the package as well as a reduction in manufacturing cost of packaging the chip element onto the wafer-board. The flip-chip bonding is conducted by use of solder bumps between the wafer-board and the chip element.
In general, the solder bumps are first provided on the wafer-board whilst solder bonding pads are provided on the chip elements at corresponding positions to the solder bumps on the wafer-board. The chip element is placed on the wafer-board before the solder bumps are heated to be melt for bonding the chip element to the wafer-board.
If the solder bumps is formed by a plating method or a press-punching method, then an oxide layer resides on a surface of each of the solder bumps, for which reason it is necessary to remove the oxide layer from the surface of the solder bump so as to permit the melt solder bump is securely bonded onto the corresponding solder bonding pad on the chip element.
FIGS. 1A through 1D are fragmentary cross sectional elevation views illustrative of wafer-boards with solder bumps to be bonded with solder bonding pads on chip elements in sequential steps involved in a conventional flip-chip bonding method of bonding a chip element onto a wafer-board.
With reference to FIG. 1A, a solder bump 2 is provided on a silicon wafer-board 1, wherein the solder bump 2 has a surface coated with an oxide layer 3.
With reference to FIG. 1B, a flux 7 is applied on the silicon wafer-board 1. Further a chip element 5 having a solder bonding pad 4 is placed over the silicon wafer-board 1 so that the solder bonding pad 4 is made into contact with a top portion of the oxide layer 3 covering the surface of the solder bump 3 on the silicon wafer-board 1 and the surface of the chip element is made into contact with the flux 7 applied on the silicon wafer-board 1 so that a gap between the silicon wafer-board 1 and the chip element 5 is filled with the flux 7. The oxide layer 3 is also in contact with the flux 7.
With reference to FIG. 1C, the silicon wafer-board 1 with the chip element 5 is subjected to a heat treatment in a reflow furnace to cause that the solder bump 2 is melt whilst the oxide layer 3 is reduced by an activation function of the flux 7.
With reference to FIG. 1D, the solder bump 2 is melt to be deformed and is made into contact directly with the solder bonding pad 4 provided on the chip element 5, whereby the chip element 5 is bonded to the silicon wafer-board 1 through the solder bump 2.
The above conventional flip-chip bonding method is disclosed in IEEE Trans. Components Hybrids and Manufacturing Technology, vol. 15, No. 6, pp. 1072-1080.
The above first conventional packaging method has the following problems.
Since the flux is used for reduction of the oxide layer on the surface of the solder bump in the heat treatment process, any component capable of causing oxidation and corrosion is likely to reside around the bump-bonding position, whereby the chip element or metal portions of the silicon wafer-board might be oxidized or corroded. As a result, deteriorations are caused of electric characteristic and properties and reliability of the packaged device.
Further, if the chip element comprises an optical device, a residue of the flux might be adhered on a light-emission area whereby an output characteristic and a sensitivity are deteriorated.
Further more, it is required that the chip element is so placed on the silicon wafer-board that the solder bump pad is made into contact with the oxide layer coating the surface of the solder bump. If the size of the solder bump is small, a highly accurate alignment of the chip element to the silicon wafer-board is also required.
In Japanese laid-open patent publication No. 6-196486, it is disclosed that a bump coated with an oxide layer is provided on a wafer-board before the bump is melt to be adhered on the wafer-board for a wet back process, wherein an ultrasonic vibration is applied to the bump for removal of the oxide layer and also causing the bump to be melt for the wet back process before a chip element is bonded through the bump onto the wafer-board without applying the ultrasonic vibration to the chip element. For this reason, the chip element is free from any problem with a damage due to the application of the ultrasonic vibration.
The above second conventional packaging method has a problem with the increase in manufacturing cost because it is required to provide an ultrasonic vibrator for applying the ultrasonic vibration to the solder bump with the oxide layer. It is further required to adjust the vibration with complicated operations for remove the oxide layer.
In Japanese laid-open patent publication No. 3-218645, it is disclosed that, without using any flux, a solder bump on a chip element is provisionally bonded onto a metal thin film provided on an electrode on a printed wiring board for subsequent immersion into a heat solution so that the solder bump is melt to bond the chip element to the printed wiring board.
The above third conventional packaging method has the following problem. If the solder bump is formed by an evaporation, the evaporation is conduced in a vacuum. To make the vacuum is costly process. If, however, the solder bump is formed by a plating method, then there are variations in plating solution concentration and current density, for which reason it is difficult to form a uniform solder bump.
Further, it is required to conduct a process of immersion of the wafer-board with the chip element into a solution such as a glycerin solution maintained at a higher temperature of, for example, 250.degree. C. than a melting point of the solder for causing the solder bump to be melt. This means it takes a further processing time to conduct the flip-chip bonding.
In the above circumstances, it had been required to develop a novel method of a flip-chip bonding between a chip element and a wafer-board through solder bumps free from the above problems.